5. PASSIVE COMPONENT INTEGRATION
The RF circuit designer must choose between on-chip and off-chip passive component integration. For low power implementation, the chosen method must provide methods to recover high performance from low power circuits reported here. The results above show that the proper choice for power and performance is for off-chip integration. Off-chip integration may first appear to present a cost disadvantage over on-chip integration. However, it is important to discuss the potential cost advantages of offchip component integration.
FOR LOW POWER
Now, passive inductors included on the CMOS die (“onchip”)suffer from substrate eddy current losses, reduced self-resonant frequency, and the possible requirements for non-standard wafer processing. For high performance, high power dissipation, broad band radio modems, low-Q circuits are compatible (or are required) for broad band fast-hopping, and high process gain systems. In contrast, for narrowband embedded radio modems, the design choice must be optimized for low bit rate and should exploit high-Q circuits.The high-Q circuits reported here have been implemented successfully with off-chip components as either low cost discrete components, in board level passive circuit patterns,or integrated into low temperature co-fired ceramic substrates. The use of bond pads carrying a ground shield between pad and substrate isolates the pads from the lossy substrate.For each integration method, cost of this off-chip integration is balanced by several issues: 1) Removing the passive components from the lossy silicon substrate drastically reduces power requirements to obtain specified performance. Therefore the high system cost associated with batteries and their prohibitive replacement cost is reduced. 2) Removing large area passive components from the chip onto the low real estate cost substrate, reduces the high cost associated with the large silicon area required for the large inductors. 3) Eliminating the requirements for non-standard CMOS technology modification required for inductors reduces development time. Finally, all RF CMOS integration methods will rely on packaging of the complete die or chipset. For packaging that relies on multichip modules, ceramic substrates, chip-on-board, and other methods, the low loss inductors reported here may be integrated with package. Thus, the incremental cost for adding low loss RF passives may be minimized.
RF电路设计者必须选择单片和off-chip被动元件之间的整合。对于低功率的实施,必须提供方法选择的方法来恢复高性能低功率电路从报告了这里。结果表明,适当选择以上电力和性能是off-chip一体化。第一次出现Off-chip整合呈现出成本劣势在单片集成。然而,重要的是潜在的成本优势,讨论offchip组件的集成。
对于低功率
现在,被动电感器包含在这个CMOS死亡(“微”)受基体涡流损耗,减少了图书的频率,和可能的要求非标晶片处理。高性能、高功率耗散、宽带无线调制解调器,low-Q电路是一致的(或被要求)fast-hopping宽带高,获得系统的过程。相比之下,对窄带嵌入式无线调制解调器,优化设计的选择一定要低比特率和应该利用高q值电路。报道了高q值电路都已经成功实施off-chip元件是用低成本分立器件,在板级电路被动模式,或融入低温co-fired陶瓷基板。使用债券垫带着一个盾牌和基材之间地垫隔离垫从有损板上。为每一个积分方法off-chip造价集成是平衡的几个问题:1)去除的无源元件的大幅度降低损耗的矽基板上的功率要求得到规定的性能。因此,高系统与成本有关电池和他们的禁止性的重置成本降低。2)去除大面积被动元件从芯片到低基质房地产成本,降低高成本相关地区大型硅所需的大电感。3)消除要求修改标准CMOS工艺所需电感降低开发时间。最后,所有的射频CMOS集成方法将依靠包装完整的死亡或芯片组。用于包装,依靠多芯片组件、陶瓷基板,chip-on-board以及其他一些方法,低损耗电感器出错可能结合包装。因此,增量成本增加低损耗射频被动可能最小化。
射频电路设计者必须选择片上和片外被动元件整合。低功耗实现，所选择的方法必须提供方法恢复高性能从低功率电路的报道。以上结果表明，选择适当的功率和性能是芯片集成。芯片集成五月一日出现目前的成本劣势在片上集成。然而，重要的是讨论的潜在成本优势的芯片组件集成。
低功率
现在，无源电感包括在半导体模具（“芯片”）遭受衬底涡流损耗，降低自谐振频率，以及可能的要求对非标的晶片处理。高性能，高功率耗散，宽带无线调制解调器，Q电路兼容的（或需要）宽带快跳频，和高处理增益系统。与此相反，窄带嵌入式无线调制解调器的设计选择，必须优化的低比特率和应利用高Q电路。高Q电路报道已经成功地实施与片外元件为低成本的离散元件，在板级电路模式，或集成到低温共烧陶瓷基板。利用债券垫进行接地屏蔽板和基板之间的隔离垫从有损衬底。每个集成方法，成本这一片集成是平衡的几个问题：1）消除无源元件的损耗的硅衬底大大降低功率要求获得特定的性能。因此，系统成本高与电池和高昂的更换成本降低。2）去除大面积无源元件的芯片上的低成本基板房地产，降低成本高与大面积所需的大电感。3）消除的要求对非标技术改造所需电感降低开发时间。最后，所有的射频集成方法将依靠包装的完整芯片或芯片组。依靠多芯片模块封装，陶瓷基板，芯片上的电路板，和其他方法，低损耗电感的报道可能集成与封装。因此，增量成本增加低损耗射频无源器件可能是最小的。
望采纳！！！！！！！1本回答被提问者采纳
RF电路设计者必须选择单片和off-chip被动元件之间的整合。对于低功率的实施,必须提供方法选择的方法来恢复高性能低功率电路从报告了这里。结果表明,适当选择以上电力和性能是off-chip一体化。第一次出现Off-chip整合呈现出成本劣势在单片集成。然而,重要的是潜在的成本优势,讨论offchip组件的集成。
对于低功率
现在,被动电感器包含在这个CMOS死亡(“微”)受基体涡流损耗,减少了图书的频率,和可能的要求非标晶片处理。高性能、高功率耗散、宽带无线调制解调器,low-Q电路是一致的(或被要求)fast-hopping宽带高,获得系统的过程。相比之下,对窄带嵌入式无线调制解调器,优化设计的选择一定要低比特率和应该利用高q值电路。报道了高q值电路都已经成功实施off-chip元件是用低成本分立器件,在板级电路被动模式,或融入低温co-fired陶瓷基板。使用债券垫带着一个盾牌和基材之间地垫隔离垫从有损板上。为每一个积分方法off-chip造价集成是平衡的几个问题:1)去除的无源元件的大幅度降低损耗的矽基板上的功率要求得到规定的性能。因此,高系统与成本有关电池和他们的禁止性的重置成本降低。2)去除大面积被动元件从芯片到低基质房地产成本,降低高成本相关地区大型硅所需的大电感。3)消除稀土
