ISE的verilog编程问题

module LED(
input clk,
input res,
output reg [7:0] led
);

reg m=0;
led=8'b00000001;

always@(posedge clk or negedge res)
begin
if(!res)
begin
if(m==0) m=1;
else m=0;
end

if(m==0)
begin
case(led_r)
8'b00000001:led=8'b00000010;
8'b00000010:led=8'b00000100;
8'b00000100:led=8'b00001000;
8'b00001000:led=8'b00010000;
8'b00010000:led=8'b00100000;
8'b00100000:led=8'b01000000;
8'b01000000:led=8'b10000000;
8'b10000000:led=8'b00000001;
endcase
end
else
begin
case(led_r)
8'b00000001:led=8'b10000000;
8'b00000010:led=8'b00000001;
8'b00000100:led=8'b00000010;
8'b00001000:led=8'b00000100;
8'b00010000:led=8'b00001000;
8'b00100000:led=8'b00010000;
8'b01000000:led=8'b00100000;
8'b10000000:led=8'b01000000;
endcase
end

end
endmodule
就是一个控制8个LED某个灯亮，然后有左移和右移两种模式，我想根据当前灯亮的情况决定一下个灯，但是编译出现问题：
ERROR:HDLCompilers:26 - "LED.v" line 29 unexpected token: '='
Module <LED> compiled
ERROR:HDLCompilers:26 - "LED.v" line 29 expecting 'endmodule', found '8'
Analysis of file <"LED.prj"> failed.
module LED(
input clk,
input res,
output reg [7:0] led=8'b00000001
);
改成这样以后，会出现问题：
ERROR:Xst:899 - "LED.v" line 35: The logic for <m> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.