数字信息在有噪信道中传输时, 会受到噪声干扰的影响, 误码总是不可避免的。为了在已知信噪比的情况下达到一定的误码率指标, 在合理设计基带信号, 选择调制、解调方式, 并采用频域均衡或时域均衡措施的基础上, 还应采用差错控制编码等信道编码技术, 使误码率进一步降低。
卷积码和分组码是差错控制编码的2 种主要形式, 在编码器复杂度相同的情况下, 卷积码的性能优于分组码,因此卷积码几乎被应用在所有无线通信的标准之中, 如GSM ,和CDMA 2000 的标准中。卷积码可以看作是将发送的信息序列通过一个线性的，有限状态的移位寄存器而产生的码，描述卷积码的方法之一是给出其生成矩阵，其编码是通过将输入信息序列与表示寄存器和模2加法器相连关系的生成矩阵进行卷积得出（Passing the information sequence to be transmitted through a linear finite-state shift register generates a convolutional code. One method of describing a convolutional code is to give its generator matrix that contains the connections of the encoder to that modulo-2 adder.）。目前, Vevilog HDL 语言已成为EDA 领域最重要的硬件设计语言之一, 越来越多的数字系统设计使用Vevilog HDL 语言来完成。原因是通过Vevilog HDL 描述的硬件系统“软核”便于存档, 程序模块的移植和ASIC 设计源程序的交付更为方便。因此, 他在IP 核的应用等方面担任着不可或缺的角色。
本设计基于Verilog 语言并使用QuartusⅡ 7.2 sp3 软件对编写的程序模块进行仿真和测试，最后输出仿真波形和程序模块。最后将本设计内容封装为IP核的形式，这样不仅方便了使用，同时也方便了在不同用户之间的移植。本设计输出的卷积器IP核具有广泛的应用领域，不仅可以广泛应用到通信领域，甚至计算机和自动控制等领域也可以广泛使用。
Convolution yard divide into groups yard control 2 main form of code mistake, in a situation that the encoder complexity is the same, the performance of yard of the convolution is superior to dividing into groups yard, so the convolution yard is nearly applied to the standard of all wireless communication, such as GSM, and in the standard of CDMA 2000. The convolution yard can be regarded as and pass the information array sent a linear one, to shift register and yard that produce limited state, describe convolution method of yard one of to provide their turn into matrix, its code is through inputting into the information array with showing register and mould 2 addition device formulation matrix linking up and concerning carry on the convolution to obtain ( Passing the information sequence to be transmitted through a linear finite-state shift register gen erates a convolutional code. One method of describing a convolutional code is to give its generator matrix that contains the conne ctions of the encoder to that modulo-2 adder.) . At present, Vevilog HDL language has already become most important hardware of EDA field to design the languages, more and more digital systems are designed and finished with Vevilog HDL languaged. The reason is through the hardware system " soft core " that Vevilog HDL is described Easy to file, it is more convenient to design the delivery of the source program in transplantation and ASIC of the module of procedure. So, he is serving as the indispensable role in such aspects as IP nuclear application.
Originally design on the basis of Verilog language and use Quartus 7.2 sp3 software to carry on emulation and test to the procedure module that is written, output the artificial wave form and procedure module finally. Will originally design the content to encapsulate for IP nuclear form finally, so it is not merely convenient to use, convenient transplantation among different users at the same time. Originally design the convolution device IP core outputted to have extensive applications, can not merely be in order to apply to communication field extensively, fields such as even the computer and automaticallying control,etc. can also be in order to use extensively.
